Integrated circuits are often designed to incorporate scan test circuitry that facilitates testing for various internal fault conditions. Such scan test circuitry typically comprises scan chains comprising multiple scan cells. The scan cells may be implemented, by way of example, utilizing respective flip-flops. The scan cells of a given scan chain are configurable to form a serial shift register for applying test patterns at inputs to combinational logic of the integrated circuit. The scan cells of the given scan chain are also used to capture outputs from other combinational logic of the integrated circuit.
Scan testing of an integrated circuit may therefore be viewed as being performed in two repeating phases, namely, a scan shift phase in which the flip-flops of the scan chain are configured as a serial shift register for shifting in and shifting out of test patterns, and a scan capture phase in which the flip-flops of the scan chain capture combinational logic outputs. These two repeating scan test phases may be collectively referred to herein as a scan test mode of operation of the integrated circuit, or as simply a scan mode of operation. Outside of the scan test mode and its scan shift and scan capture phases, the integrated circuit may be said to be in a functional mode of operation. Other definitions of the scan test and functional operating modes may also be used.
An integrated circuit may also be configured to include built-in self-test (BIST) capabilities. Such BIST capabilities in some implementations make use of scan test circuitry and operating modes of the type described above. BIST implementations may be configured to test particular portions of an integrated circuit, such as a memory. BIST testing of integrated circuit memories is also referred to as memory BIST (MBIST). MBIST is typically used to detect faults that are internal to the memory. However, conventional MBIST arrangements are unable to detect faults associated with functional data and address paths at the memory interface. This is because the data and address inputs applied during MBIST are provided to the memory interface by an MBIST controller, with the functional data and address paths bypassed. Undetected faults associated with these functional paths at the memory interface can cause the integrated circuit to fail in the field.